The present invention relates to three-dimensional (3D) microelectronic device processing, and more particular to a method of fabricating at least one opening, e.g., trench or via, in a substrate wherein a thin, uniform thermal nitride vertical hard mask, which prohibits diffusion of dopants into the substrate, is formed on at least an upper portion of exposed sidewalls of the opening. The present invention is also directed to 3D microelectronic structures which include the above-mentioned thin, uniform thermal nitride mask on at least an upper portion of exposed sidewalls of an opening formed in a substrate.
Trench or via processing for three-dimensional (3D) microelectronic fabrication, e.g., dynamic random access memory (DRAM) cells, includes making of a portion of a trench or via for p-n junction definition by diffusion; non-uniform (enhanced) doping of selected areas; and formation of electrical isolation regions in selected areas. Therefore, a masking method is needed to select portions of a trench or via for desired processing.
In general, masking processes require the use of a hard mask (planar or vertical) to protect selected portions of the substrate against doping, etching, oxidation, deposition, implantation, and other processing. Contrary to a photoresist (PR) and other polymer masks, hard masks are able to withstand high-temperature processing. In addition, hard masks may have a higher etch selectivity than that of a polymer mask.
The fabrication sequence for a planar hard mask is straightforward. First, a hard mask material is deposited over an entire surface of a substrate and thereafter a patterned PR mask is formed over the hard mask using conventional photolithographic methods. Next, the hard mask material is removed from selected areas utilizing a selective etching process. Consequently, the remaining planar hard mask material protects pre-selected areas of the substrate.
The fabrication sequence of a vertical hard mask, on the other hand, is complicated. Indeed, there are no known photolithography methods that would leave photoresist in the upper portion of a trench or via and remove resist from the bottom portion-of the trench or via. The vertical hard masks are typically made utilizing the following five steps: (i) depositing a sacrificial material into an opening of a 3D microelectronic structure; (ii) planarizing the sacrificial material; (iii) recessing the sacrificial material to a predetermined depth; (iv) forming a hard mask on an upper portion of the opening; and (v) removing the sacrificial material from the opening.
There are several requirements for using vertical hard masks which include: (1) a vertical hard mask should be suitable for use with high-temperature (about 300xc2x0-100xc2x0 C.) processing and the vertical hard mask should not loose its masking properties at the above-mentioned high-temperatures; (2) the vertical hard mask should be substantially thin (as compared to the mouth of the trench or via) so that the hard mask does not interfere with the deposition of various materials into the trench or via; and (3) the process sequence needed to create such a hard mask must be relatively simple.
One standard way of producing a vertical hard mask for lining at least a portion of a trench or via is to use a thin oxide grown on an exposed surface of a Si-containing substrate, while protecting selected areas with deposited silicon nitride. Because silicon nitride oxidizes very slowly one can grow a relatively thick layer of thermal oxide on the Si-containing substrate, while oxidizing only several atomic layers of silicon nitride. Subsequently, silicon nitride is stripped selectively to the thick oxide layer grown on the Si-containing substrate.
There are several problems with using such an approach. A vertical mask comprising a thermally grown oxide layer is not a good diffusion barrier; therefore, the thermal oxide mask has to be grown relatively thick in order to block dopant diffusion. For narrow openings, i.e., trenches or vias, the thickness of the oxide mask can be comparable to the dimensions of the opening preventing a good fill into the trench or via. In addition, thermally grown oxide masks are not typically uniform along the perimeter of the opening (the thermally grown oxide is usually thinner at the corners). Such non-uniformity is due to the different oxidation rate of different crystallographic planes of silicon and build-up of stress in the corners.
One known modification to the oxide mask process described above is directed towards thermal nitridation of the oxide mask. When nitrogen is introduced into a thermally grown oxide mask, the nitrogen reduces diffusion of dopants through the thermal oxide layer. Due to a high chemically stability of the thermally grown oxide layer only a small percentage (typically below 20 atomic percent) of nitrogen atoms is incorporated into the thermal oxide mask. Therefore, the oxynitride or nitrided oxide mask has to be relatively thick to block dopant diffusion at high temperatures.
In view of the above drawbacks with thermally grown oxide vertical masks, a new and improved method is required to form a thin, uniform vertical hard mask, which functions as a diffusion barrier so as to prevent unwanted diffusion of dopant into substrate during p-n junction definition.
One object of the present invention is to provide a method for fabricating 3D microelectronic structures which include at least one opening present in a substrate wherein a vertical hard mask which is resistant to high-temperature processing is employed.
Another object of the present invention is to provide a method for fabricating 3D microelectronic structures which include at least one opening present in a substrate wherein a substantially thin vertical hard mask is employed to protect selective portions of the opening.
A further object of the present invention is to provide a method of fabricating 3D microelectronic structures which include at least one opening present in a substrate wherein simple processing steps are employed to form a vertical hard mask on at least an upper portion of exposed sidewalls of the at least one opening.
A yet further object of the present invention is to provide a method of fabricating 3D microelectronic structures which include at least one opening present in a semiconductor substrate wherein a thin, uniform vertical hard mask is formed on an upper portion of exposed sidewalls of the at least one opening.
These and other objects and advantages are achieved in the present invention by forming a thermal nitride vertical hard mask on at least an upper portion of exposed interior sidewalls of an opening formed in a substrate (either semiconducting or insulating). The thermal nitride employed in the present invention is substantially thin, on the order of from about 10 to about 50 xc3x85, and the thermal nitride is a very good dopant diffusion barrier material. The inventive method employed in forming the thermal nitride vertical hard mask is relatively simple and easy to implement with existing semiconductor device processing schemes.
In one aspect of the present invention, a 3D microelectronic structure containing a thin thermal nitride hard mask on selective portions of an opening formed in a substrate is provided. In broad terms, the 3D microelectronic structure of the present invention comprises:
a substrate having at least one opening present therein, said at least one opening having sidewalls which extend to a common bottom wall; and
a thermal nitride layer present on at least an upper portion of each sidewall of said at least one opening.
Another aspect of the present invention comprises a method for fabricating the abovementioned 3D microelectronic structure. Specifically, the inventive method comprises the steps of:
(a) forming at least one opening in a surface of a substrate, said at least one opening having sidewalls which extend to a common bottom wall; and
(b) forming a thermal nitride layer on at least an upper portion of each sidewall of said at least one opening.